Ahb/Apb Bridges (Apb); Memory Organization; Memory Map; Table 2. Stm32F4Xx Register Boundary Addresses - ST STM32F40 Series Reference Manual

RM0090
2.1.9

AHB/APB bridges (APB)

The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between
the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.
Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies,
and to Table 2 on page 52
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash
memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR or RCC_APBxENR register.
Note: When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
2.2

Memory organization

Program memory, data memory, registers and I/O ports are organized within the same linear
4 Gbyte address space.
The bytes are coded in memory in little endian format. The lowest numbered byte in a word
is considered the word's least significant byte and the highest numbered byte, the word's
most significant.
For the detailed mapping of peripheral registers, please refer to the related chapters.
The addressable memory space is divided into 8 main blocks, each of 512 MB.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered "Reserved"). Refer to the memory map figure in the product datasheet.
2.3

Memory map

See the datasheet corresponding to your device for a comprehensive diagram of the
memory map.
STM32F4xx devices.
Table 2. STM32F4xx register boundary addresses
Boundary address
0xA000 0000 - 0xA000 0FFF FSMC control register AHB3
0x5006 0800 - 0x5006 0BFF
0x5006 0400 - 0x5006 07FF
0x5006 0000 - 0x5006 03FF
0x5005 0000 - 0x5005 03FF
0x5000 0000 - 0x5003 FFFF
for the address mapping of AHB and APB peripherals.
Table 2 gives the boundary addresses of the peripherals available in all
Peripheral
RNG
HASH
CRYP
DCMI
USB OTG FS
Doc ID 018909 Rev 4
Bus
Section 32.6.9: FSMC register map on page 1373
Section 21.4.4: RNG register map on page 598
Section 22.4.9: HASH register map on page 622
Section 20.6.13: CRYP register map on page 591
AHB2
Section 13.8.12: DCMI register map on page 351
Section 30.16.6: OTG_FS register map on
page 1106
Memory and bus architecture
Register map
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