Figure 169. Counter Timing Diagram, Internal Clock Divided By 1; Figure 170. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F40 Series Reference Manual

General-purpose timers (TIM9 to TIM14)
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
●
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
●
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 169. Counter timing diagram, internal clock divided by 1

Figure 170. Counter timing diagram, internal clock divided by 2

487/1422
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 018909 Rev 4
31 32 33 34 35 36 00 01 02 03 04 05 06 07
0034
0035 0036 0000 0001 0002 0003
RM0090