Table 108. Error Calculation For Programmed Baud Rates At F - ST STM32F40 Series Reference Manual

RM0090
The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000
How to derive USARTDIV from USART_BRR register values when OVER8=1
Example 1:
If DIV_Mantissa = 0x27 and DIV_Fraction[2:0]= 0d6 (USART_BRR = 0x1B6), then
Mantissa (USARTDIV) = 0d27
Fraction (USARTDIV) = 6/8 = 0d0.75
Therefore USARTDIV = 0d27.75
Example 2:
To program USARTDIV = 0d25.62
This leads to:
DIV_Fraction = 8*0d0.62 = 0d4.96
The nearest real number is 0d5 = 0x5
DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19
Then, USART_BRR = 0x195 => USARTDIV = 0d25.625
Example 3:
To program USARTDIV = 0d50.99
This leads to:
DIV_Fraction = 8*0d0.99 = 0d7.92
The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x0330 => USARTDIV = 0d51.000

Table 108. Error calculation for programmed baud rates at f

oversampling by 16
Baud rate7
S.No Desired
1 1.2 KBps
2 2.4 KBps
3 9.6 KBps
4 19.2 KBps 19.185 KBps
Universal synchronous asynchronous receiver transmitter (USART)
(1)
Oversampling by 16 (OVER8=0)
f = 8 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
1.2 KBps 416.6875
2.4 KBps 208.3125
9.604 KBps 52.0625
26.0625
Doc ID 018909 Rev 4
= 8 MHz or f
PCLK
% Error =
(Calculated -
Actual
Desired) B.rate /
Desired B.rate
0 1.2 KBps
0.01 2.4 KBps
0.04 9.6 KBps
0.08 19.2 KBps
= 12 MHz,
PCLK
f = 12 MHz
PCLK
Value
programmed
% Error
in the baud
rate register
625 0
312.5 0
78.125 0
39.0625 0
756/1422