Tim9/12 Slave Mode Control Register (Timx_Smcr) - ST STM32F40 Series Reference Manual

RM0090
16.5.3

TIM9/12 slave mode control register (TIMx_SMCR)

Address offset: 0x08
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/Slave mode
Bits 6:4 TS: Trigger selection
Note: These bits must be changed only when they are not used (e.g. when SMS='000') to
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input
12 11 10 9
Reserved
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful in
order to synchronize several timers on a single external event.
This bitfield selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: Reserved.
See Table 79: TIMx internal trigger connection on page 505
of ITRx for each timer.
avoid wrong edge detections at the transition.
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input control register and Control register
descriptions.
000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
clock
001: Reserved
010: Reserved
011: Reserved
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and
stops are both controlled
110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter
(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
Gated mode checks the level of the trigger signal.
Doc ID 018909 Rev 4
General-purpose timers (TIM9 to TIM14)
8 7 6 5
MSM TS[2:0]
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4 3 2 1
SMS[2:0]
Res.
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for more details on the meaning
0
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