ST STM32F40 Series Reference Manual page 762

RM0090
Table 115. Error calculation for programmed baud rates at f
oversampling by 8
Baud rate
S.No Desired
3. 19.2 KBps
4. 57.6 KBps
5. 115.2 KBps
6. 230.4 KBps
7. 460.8 KBps
8. 896 KBps
9. 921.6 KBps
10. 1.792 MBps
11. 1.8432 MBps
12. 3.584 MBps
13. 3.6864 MBps
14. 7.168 MBps
15. 7.3728 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
Table 116. Error calculation for programmed baud rates at f
oversampling by 16
Baud rate
S.No Desired
1 1.2 KBps
2 2.4 KBps
3 9.6 KBps
4 19.2 KBps
5 38.4 KBps
6 57.6 KBps
7 115.2 KBps
Universal synchronous asynchronous receiver transmitter (USART)
(1) (2)
(continued)
Oversampling by 8 (OVER8=1)
f = 30 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
19.194 KBps 195.3750
57.582 KBps 65.1250
115.385 KBps 32.5000
230.769 KBps 16.2500
461.538 KBps 8.1250
909.091 KBps 4.1250
909.091 KBps 4.1250
1.7647 MBps 2.1250
1.8750 MBps 2.0000
3.7500 MBps 1.0000
3.7500 MBps 1.0000
NA NA
NA NA
(1)(2)
Oversampling by 16 (OVER8=0)
f = 42 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
1.2 KBps 2187.5
2.4 KBps 1093.75
9.6 KBps 273.4375
19.195 KBps 136.75
38.391 KBps 68.375
57.613 KBps 45.5625
115.068 KBps 22.8125
Doc ID 018909 Rev 4
= 30 MHz or f
PCLK
% Error =
(Calculated -
Actual
Desired)B.Rate
/Desired B.Rate
0.03% 19.200 KBps
0.16% 57.582 KBps
0.16% 115.163 KBps 65.1250
0.16% 230.769 KBps 32.5000
0.16% 461.538 KBps 16.2500
1.46% 895.522 KBps 8.3750
1.36% 923.077 KBps 8.1250
1.52% 1.8182 MBps
1.73% 1.8182 MBps
4.63% 3.5294 MBps
1.73% 3.7500 MBps
NA 7.5000 MBps
NA 7.5000 MBps
= 42 MHz or f
PCLK
% Error =
(Calculated -
Actual
Desired)B.Rate
/Desired B.Rate
0 1.2 KBps
0 2.4 KBps
0 9.6 KBps
0.02 19.2 KBps
0.02 38.391 KBps
0.02 57.613 KBps
0.11 115.226 KBps
= 60 MHz,
PCLK
f =60 MHz
PCLK
Value
programmed
% Error
in the baud
rate register
390.6250 0.00%
130.2500 0.03%
0.03%
0.16%
0.16%
0.05%
0.16%
4.1250 1.46%
4.1250 1.36%
2.1250 1.52%
2.0000 1.73%
1.0000 4.63%
1.0000 1.73%
= 84 Hz,
PCLK
f = 84 MHz
PCLK
Value
programmed
% Error
in the baud
rate register
4375 0
2187.5 0
546.875 0
273.4375 0
136.75 0.02
91.125 0.02
45.5625 0.02
762/1422