Timer Synchronization; Figure 159. Master/Slave Timer Example - ST STM32F40 Series Reference Manual

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General-purpose timers (TIM2 to TIM5)

Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When

one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of

another Timer configured in Slave Mode.

Figure 159: Master/Slave timer example

the master mode selection blocks.

Using one timer as prescaler for another

For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to

159. To do this:

Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each

update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is

output on TRGO1 each time an update event is generated.

To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in

slave mode using ITR0 as internal trigger. You select this through the TS bits in the

TIM2_SMCR register (writing TS=000).

Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the

TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the

periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).

Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1

If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock

the counter of timer 2.

Using one timer to enable another timer

In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.

for connections. Timer 2 counts on the divided internal clock only when

Doc ID 018909 Rev 4

presents an overview of the trigger selection and

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