Sdio Apb2 Interface; Table 135. Receive Fifo Status Flags - ST STM32F40 Series Reference Manual

RM0090

Table 135. Receive FIFO status flags

Flag
RXFIFOF
RXFIFOE
RXFIFOHF
RXDAVL
RXOVERR
28.3.2

SDIO APB2 interface

The APB2 interface generates the interrupt and DMA requests, and accesses the SDIO
adapter registers and the data FIFO. It consists of a data path, register decoder, and
interrupt/DMA logic.
SDIO interrupts
The interrupt logic generates an interrupt request signal that is asserted when at least one
of the selected status flags is high. A mask register is provided to allow selection of the
conditions that will generate an interrupt. A status flag generates the interrupt request if a
corresponding mask flag is set.
SDIO/DMA interface - procedure for data transfers between the SDIO and
memory
In the example shown, the transfer is from the SDIO host controller to an MMC (512 bytes
using CMD24 (WRITE_BLOCK). The SDIO FIFO is filled by data stored in a memory using
the DMA controller.
1. Do the card identification process
2. Increase the SDIO_CK frequency
3. Select the card by sending CMD7
4. Configure the DMA2 as follows:
a)
b)
c)
d)
e)
f)
Set to high when all 32 receive FIFO words contain valid data
Set to high when the receive FIFO does not contain valid data.
Set to high when 8 or more receive FIFO words contain valid data. This flag can be
used as a DMA request.
Set to high when the receive FIFO is not empty. This flag is the inverse of the
RXFIFOE flag.
Set to high when an overrun error occurs. This flag is cleared by writing to the SDIO
Clear register.
Enable DMA2 controller and clear any pending interrupts.
Program the DMA2_Stream3 or DMA2_Stream6 Channel4 source address
register with the memory location's base address and DMA2_Stream3 or
DMA2_Stream6 Channel4 destination address register with the SDIO_FIFO
register address.
Program DMA2_Stream3 or DMA2_Stream6 Channel4 control register (memory
increment, not peripheral increment, peripheral and source width is word size).
Program DMA2_Stream3 or DMA2_Stream6 Channel4 to select the peripheral as
flow controller (set PFCTRL bit in DMA_S3CR or DMA_S6CR configuration
register).
Configure the incremental burst transfer to 4 beats (at least from peripheral side)
in DMA2_Stream3 or DMA2_Stream6 Channel4.
Enable DMA2_Stream3 or DMA2_Stream6 Channel4
Doc ID 018909 Rev 4
Secure digital input/output interface (SDIO)
Description
860/1422