ST STM32F40 Series Reference Manual page 736

RM0090
Bit 1 ADDR: Address sent (master mode)/matched (slave mode)
Note: In slave mode, it is recommended to perform the complete clearing sequence (READ
Note: ADDR is not set after a NACK reception
Bit 0 SB: Start bit (Master mode)
This bit is cleared by software reading SR1 register followed reading SR2, or by hardware
when PE=0.
Address matched (Slave)
0: Address mismatched or not received.
1: Received address matched.
–Set by hardware as soon as the received slave address matched with the OAR registers
content or a general call or a SMBus Device Default Address or SMBus Host or SMBus
Alert is recognized. (when enabled depending on configuration).
SR1 then READ SR2) after ADDR is set. Refer to
diagram for slave receiver on page
Address sent (Master)
0: No end of address transmission
1: End of address transmission
–For 10-bit addressing, the bit is set after the ACK of the 2nd byte.
–For 7-bit addressing, the bit is set after the ACK of the byte.
0: No Start condition
1: Start condition generated.
–Set when a Start condition generated.
–Cleared by software by reading the SR1 register followed by writing the DR register, or by
hardware when PE=0
Doc ID 018909 Rev 4
Inter-integrated circuit (I
Figure 242: Transfer sequence
714.
2
C) interface
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