Figure 134. Counter Timing Diagram, Internal Clock Divided By 2; Figure 135. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 136. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F40 Series Reference Manual

RM0090

Figure 134. Counter timing diagram, internal clock divided by 2

Figure 135. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 136. Counter timing diagram, internal clock divided by N

CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow (cnt_ovf)
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 018909 Rev 4
General-purpose timers (TIM2 to TIM5)
0003
0002 0001 0000 0001 0002 0003
0034 0035
20
1F 01
0036 0035
00
432/1422