Media-Independent Interface: Mii; Table 162. Clock Range; Figure 325. Media Independent Interface Signals - ST STM32F40 Series Reference Manual

RM0090
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 162

Table 162. Clock range

100, 101, 110, 111
29.4.2

Media-independent interface: MII

The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.

Figure 325. Media independent interface signals

●
MII_TX_CLK: continuous clock that provides the timing reference for the TX data
transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s
speed.
●
MII_RX_CLK: continuous clock that provides the timing reference for the RX data
transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s
speed.
● MII_TX_EN: transmission enable indicates that the MAC is presenting nibbles on the
MII for transmission. It must be asserted synchronously (MII_TX_CLK) with the first
nibble of the preamble and must remain asserted while all nibbles to be transmitted are
presented to the MII.
●
MII_TXD[3:0]: transmit data is a bundle of 4 data signals driven synchronously by the
MAC sublayer and qualified (valid data) on the assertion of the MII_TX_EN signal.
Ethernet (ETH): media access control (MAC) with DMA controller
shows how to set the clock ranges.
Selection
000
001
010
011
STM32
Doc ID 018909 Rev 4
HCLK clock
60-100 MHz
100-168 MHz
20-35 MHz
35-60 MHz
Reserved
TX _CLK
TXD[3:0]
TX_EN
RX_CLK
RXD[3:0]
External
RX_ER
RX_DV
CRS
COL
MDC
MDIO
MDC clock
AHB clock / 42
AHB clock / 62
AHB clock / 16
AHB clock / 26
-
PHY
ai15622b
910/1422