Arbiter; Table 36. Dma2 Request Mapping - ST STM32F40 Series Reference Manual

DMA controller (DMA)
Table 35. DMA1 request mapping (continued)
Peripheral
Stream 0
requests
TIM5_CH3
Channel 6
TIM5_UP
Channel 7
1. These requests are available on STM32F42xxx and STM32F43xxx only.
Table 36. DMA2 request mapping
Peripheral
Stream 0
requests
Channel 0
ADC1
Channel 1
Channel 2 ADC3
Channel 3
SPI1_RX
(1)
Channel 4 SPI4_RX
Channel 5
Channel 6 TIM1_TRIG
Channel 7
1. These requests are available on STM32F42xxx and STM32F43xxx.
9.3.4

Arbiter

An arbiter manages the 8 DMA stream requests based on their priority for each of the two
AHB master ports (memory and peripheral ports) and launches the peripheral/memory
access sequences.
Priorities are managed in two stages:
●
Software: each stream priority can be configured in the DMA_SxCR register. There are
four levels:
–
–
–
–
●
Hardware: If two requests have the same software priority level, the stream with the
lower number takes priority over the stream with the higher number. For example,
Stream 2 takes priority over Stream 4.
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Stream 1 Stream 2
TIM5_CH4
TIM5_CH1
TIM5_TRIG
TIM6_UP I2C2_RX
Stream 1 Stream 2
TIM8_CH1
TIM8_CH2
TIM8_CH3
DCMI ADC2
ADC3
SPI1_RX
(1)
SPI4_TX
USART1_RX
USART6_RX USART6_RX
TIM1_CH1 TIM1_CH2
TIM8_UP TIM8_CH1
Very high priority
High priority
Medium priority
Low priority
Doc ID 018909 Rev 4
Stream 3 Stream 4
TIM5_CH4
TIM5_CH2
TIM5_TRIG
USART3_TX
I2C2_RX
Stream 3 Stream 4
ADC1
ADC2
(1) (1)
SPI5_RX SPI5_TX
SPI1_TX
SDIO
(1) (1)
SPI4_RX SPI4_TX
TIM1_CH4
TIM1_CH1 TIM1_TRIG
TIM1_COM
TIM8_CH2 TIM8_CH3
Stream 5 Stream 6
TIM5_UP
DAC1 DAC2
Stream 5 Stream 6
TIM1_CH1
TIM1_CH2
TIM1_CH3
(1) (1)
SPI6_TX SPI6_RX
CRYP_OUT CRYP_IN
SPI1_TX
USART1_RX SDIO
USART6_TX
TIM1_UP TIM1_CH3
(1) (1)
SPI5_RX SPI5_TX
RM0090
Stream 7
I2C2_TX
Stream 7
DCMI
HASH_IN
USART1_TX
USART6_TX
TIM8_CH4
TIM8_TRIG
TIM8_COM