Rcc Apb1 Peripheral Reset Register For; Stm32F42Xxx And Stm32F43Xxx (Rcc_Apb1Rstr) - ST STM32F40 Series Reference Manual

RM0090
6.3.9

RCC APB1 peripheral reset register for

STM32F42xxx and STM32F43xxx (RCC_APB1RSTR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
UART8R UART7R PWR
DACRST
ST ST RST
rw rw rw
15 14 13
SPI3 SPI2
RST RST
Reserved
rw rw
Bits 31 UART8RST: UART8 reset
Set and cleared by software.
0: does not reset UART8
1: resets UART8
Bits 30 UART7RST: UART7 reset
Set and cleared by software.
0: does not reset UART7
1: resets UART7
Bit 29 DACRST: DAC reset
Set and cleared by software.
0: does not reset the DAC interface
1: resets the DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: does not reset the power interface
1: resets the power interface
Bit 27 Reserved, must be kept at reset value.
Bit 26 CAN2RST: CAN2 reset
Set and cleared by software.
0: does not reset CAN2
1: resets CAN2
Bit 25 CAN1RST: CAN1 reset
Set and cleared by software.
0: does not reset CAN1
1: resets CAN1
Bit 24 Reserved, must be kept at reset value.
Bit 23 I2C3RST: I2C3 reset
Set and cleared by software.
0: does not reset I2C3
1: resets I2C3
28 27 26 25
CAN2 CAN1
Reser-
RST RST
ved
rw rw
12 11 10 9
WWDG
RST
Reserved
rw
Doc ID 018909 Rev 4
24 23 22 21
I2C3 I2C2 I2C1
Reser-
RST RST RST
ved
rw rw rw
8 7 6
TIM14 TIM13 TIM12 TIM7
RST RST RST RST
rw rw rw rw
Reset and clock control for (RCC)
20 19 18
UART5 UART4 UART3
RST RST RST
rw rw rw
5 4 3 2
TIM6 TIM5 TIM4
RST RST RST
rw rw rw
17 16
UART2
Reser-
RST
ved
rw
1 0
TIM3 TIM2
RST RST
rw rw
138/1422