Flash Option Control Register (Flash_Optcr1); For Stm32F42Xxx And Stm32F43Xxx - ST STM32F40 Series Reference Manual

Embedded Flash memory interface
Bits 3:2 BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level. By default, BOR is off. When the supply voltage (V
drops below the selected BOR level, a device reset is generated.
00: BOR Level 3 (VBOR3), reset threshold level for 2.70 to 3.60 V voltage range
01: BOR Level 2 (VBOR2), reset threshold level for 2.40 to 2.70 V voltage range
10: BOR Level 1 (VBOR1), reset threshold level for 2.10 to 2.40 V voltage range
11: BOR off (VBOR0), reset threshold level for 1.80 to 2.10 V voltage range
Note: For full details about BOR characteristics, refer to the "Electrical characteristics" section
Bit 1 OPTSTRT: Option start
This bit triggers a user option operation when set. It is set only by software and cleared when
the BSY bit is cleared.
Bit 0 OPTLOCK: Option lock
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked.
This bit is cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
3.8.8

Flash option control register (FLASH_OPTCR1)

for STM32F42xxx and STM32F43xxx

This register is available only on STM32F42xxx and STM32F43xxx.
The FLASH_OPTCR1 register is used to modify the user option bytes for sectors 12 to 23.
Address offset: 0x18
Reset value: 0x0FFF 0000. The option bits are loaded with values from Flash memory at
reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31 30 29
Reserved
15 14 13
Bits 31:28 Reserved, must be kept cleared.
Bits 27:16 nWRP: Not write protect
These bits contain the value of the write-protection option bytes for sectors 12 to 23 after
reset. They can be written to program a new write protect value into Flash memory.
0: Write protection active
1: Write protection not active
Bits 15:0 Reserved, must be kept cleared.
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in the device datasheet.
28 27 26 25
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12 11 10 9
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24 23 22 21
nWRP[11:0]
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8 7 6 5
Reserved
20 19 18 17
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4 3 2 1
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0