Context Swapping - ST STM32F40 Series Reference Manual

Cryptographic processor (CRYP)
3. All the transfers and processing are managed by the DMA and the cryptographic
processor. The DMA interrupt indicates that the processing is complete. Both FIFOs
are normally empty and BUSY = 0.
Processing when the data are transferred by the CPU during interrupts
1. Enable the interrupts by setting the INIM and OUTIM bits in the CRYP_IMSCR register.
2. Enable the cryptographic processor by setting the CRYPEN bit in the CRYP_CR
register.
3. In the interrupt managing the input data: load the input message into the IN FIFO. You
can load 2 or 4 words at a time, or load data until the FIFO is full. When the last word of
the message has been entered into the FIFO, disable the interrupt by clearing the INIM
bit.
4. In the interrupt managing the output data: read the output message from the OUT
FIFO. You can read 1 block (2 or 4 words) at a time or read data until the FIFO is empty.
When the last word has been read, INIM=0, BUSY=0 and both FIFOs are empty
(IFEM=1 and OFNE=0). You can disable the interrupt by clearing the OUTIM bit and,
the peripheral by clearing the CRYPEN bit.
Processing without using the DMA nor interrupts
1. Enable the cryptographic processor by setting the CRYPEN bit in the CRYP_CR
register.
2. Write the first blocks in the input FIFO (2 to 8 words).
3. Repeat the following sequence until the complete message has been processed:
a)
b)
4. At the end of the processing, BUSY=0 and both FIFOs are empty (IFEM=1 and
OFNE=0). You can disable the peripheral by clearing the CRYPEN bit.
20.3.7

Context swapping

If a context switching is needed because a new task launched by the OS requires this
resource, the following tasks have to be performed for full context restoration (example when
the DMA is used):
Case of the AES and DES
1. Context saving
a)
b)
c)
d)
573/1422
Wait for OFNE=1, then read the OUT-FIFO (1 block or until the FIFO is empty)
Wait for IFNF=1, then write the IN FIFO (1 block or until the FIFO is full)
Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR
register.
Wait until both the IN and OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
CRYP_SR register) and the BUSY bit is cleared.
Stop DMA transfers on the OUT FIFO by writing the DOEN bit to 0 in the
CRYP_DMACR register and clear the CRYPEN bit.
Save the current configuration (bits [9:2] and bits 19 in the CRYP_CR register)
and, if not in ECB mode, the initialization vectors. The key value must already be
available in the memory. When needed, save the DMA status (pointers for IN and
OUT messages, number of remaining bytes, etc.).
Doc ID 018909 Rev 4
RM0090