Flash Interface Registers; Flash Access Control Register (Flash_Acr) - ST STM32F40 Series Reference Manual

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Embedded Flash memory interface

The OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16

bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes

LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP

data block can be programmed until the value 0x00 is programmed in the corresponding

OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP

bytes might not be taken into account correctly.

Flash interface registers

The Flash access control register is used to enable/disable the acceleration features and

control the Flash memory access time according to CPU frequency.

Address offset: 0x00

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:11 Reserved, must be kept cleared.

Bit 12 DCRST: Data cache reset

Bit 11 ICRST: Instruction cache reset

Bit 10 DCEN: Data cache enable

Bit 9 ICEN: Instruction cache enable

OTP area organization (continued)

0: Data cache is not reset

1: Data cache is reset

This bit can be written only when the D cache is disabled.

0: Instruction cache is not reset

1: Instruction cache is reset

This bit can be written only when the I cache is disabled.

0: Data cache is disabled

1: Data cache is enabled

0: Instruction cache is disabled

1: Instruction cache is enabled

Doc ID 018909 Rev 4

Address byte 0

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