I 2 S Master Mode; Table 125. Audio Frequency Precision (For Pllm Vco = 1 Mhz Or 2 Mhz) - ST STM32F40 Series Reference Manual

RM0090

Table 125. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz)

Master Target f
S
clock (Hz)
8000
16000
32000
48000
Disabled
96000
22050
44100
192000
8000
16000
32000
Enabled 48000
96000
22050
44100
1. This table gives only example values for different clock configurations. Other configurations allowing optimum clock
precision are possible.
2
27.4.5 I S master mode
2
The I S can be configured as follows:
● In master mode for transmission or reception (half-duplex mode using I2Sx)
●
In master mode transmission and reception (full duplex mode using I2Sx and
I2Sx_ext).
This means that the serial clock is generated on the CK pin as well as the Word Select
signal WS. Master clock (MCK) may be output or not, thanks to the MCKOE bit in the
SPI_I2SPR register.
Data
PLLI2SN
format
16-bit 192
32-bit 192
16-bit 192
32-bit 256
16-bit 256
32-bit 256
16-bit 192
32-bit 384
16-bit 384
32-bit 424
16-bit 290
32-bit 302
16-bit 302
32-bit 429
16-bit 424
32-bit 258
don't care 256
don't care 213
don't care 213
don't care 258
don't care 344
don't care 429
don't care 271
Doc ID 018909 Rev 4
PLLI2SR I2SDIV I2SODD
2 187
3 62
3 62
2 62
2 62
5 12
5 12
5 12
5 12
3 11
3 68
2 53
2 53
4 19
3 11
3 3
5 12
2 13
2 6
3 3
2 3
4 9
2 6
Serial peripheral interface (SPI)
(1)
Real f (Hz)
S
1 8000
1 8000
1 16000
1 16000
1 32000
1 32000
1 48000
1 48000
1 96000
1 96014.49219
1 22049.87695
1 22050.23438
1 44100.46875
0 44099.50781
1 192028.9844
1 191964.2813
1 8000
0 16000.60059
1 32001.20117
1 47991.07031
1 95982.14063
1 22049.75391
0 44108.07422
Error
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0151%
0.0006%
0.0011%
0.0011%
0.0011%
0.0151%
0.0186%
0.0000%
0.0038%
0.0038%
0.0186%
0.0186%
0.0011%
0.0183%
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