Figure 41. Multi Adc Block Diagram - ST STM32F40 Series Reference Manual

RM0090

Figure 41. Multi ADC block diagram

ADCx_IN0
ADCx_IN1
ADCx_IN15
EXTI_11
EXTI_15
1. Although external triggers are present on ADC2 and ADC3 they are not shown in this diagram.
2. In the Dual ADC mode, the ADC3 slave part is not present.
3. In Triple ADC mode, the ADC common data register (ADC_CDR) contains the ADC1, ADC2 and ADC3's
regular converted data. All 32 register bits are used according to a selected storage order.
In Dual ADC mode, the ADC common data register (ADC_CDR) contains both the ADC1 and ADC2's
regular converted data. All 32 register bits are used.
GPIO
Ports
Temp. sensor
V
REFINT
V
BAT
Start trigger mux
(regular group)
Start trigger mux
(injected group)
Doc ID 018909 Rev 4
Analog-to-digital converter (ADC)
(1)
Regular data register
(12 bits)
(16 bits)
Regular
channels
Injected
channels
Regular data register
(12 bits)
Regular
channels
Injected
channels
internal triggers
Common regular data register
(32 bits)
Dual/Triple
mode control
Regular data register
(16 bits)
Regular
channels
Injected
channels
ADC1 (Master)
Injected data registers
(4 x 16 bits)
(2)
ADC3 (Slave)
(16 bits)
Injected data registers
(4 x 16 bits)
ADC2 (Slave)
(3)
Common part
Injected data registers
(4 x 16 bits)
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