Timx Dma/Interrupt Enable Register (Timx_Dier); Table 76. Timx Internal Trigger Connection - ST STM32F40 Series Reference Manual

RM0090
Table 76.
Slave TIM
TIM4
TIM5
15.4.4

TIMx DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
TDE CC4DE CC3DE CC2DE CC1DE
Res. Res
rw
Bit 15
Bit 14 TDE: Trigger DMA request enable
Bit 13
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
Bit 8 UDE: Update DMA request enable
Bit 7
Bit 6 TIE: Trigger interrupt enable
Bit 5
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
TIMx internal trigger connection
ITR0 (TS = 000)
TIM1
TIM2
12 11 10 9
rw rw rw rw
Reserved, must be kept at reset value.
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Reserved, always read as 0
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
0: Update DMA request disabled.
1: Update DMA request enabled.
Reserved, must be kept at reset value.
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Reserved, must be kept at reset value.
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Doc ID 018909 Rev 4
General-purpose timers (TIM2 to TIM5)
ITR1 (TS = 001)
TIM2
TIM3
8 7 6 5
UDE TIE
Res. Res
rw rw
ITR2 (TS = 010) ITR3 (TS = 011)
TIM3
TIM4
4 3 2
CC4IE CC3IE CC2IE
rw rw rw
TIM8
TIM8
1 0
CC1IE UIE
rw rw
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