How To Program The Watchdog Timeout; Figure 272. Window Watchdog Timing Diagram - ST STM32WL5 Series Reference Manual

System window watchdog (WWDG)
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
31.3.5

How to program the watchdog timeout

Use the formula in
Warning:
CNT DownCounter
T[6:0]
W[6:0]
0x3F
wwdg_ewit
wwdg_rst
T6 bit
The formula to calculate the timeout value is given by:
where:
t
WWDG
t
PCLK
4096: value corresponding to internal divider
994/1461
Figure 272 to calculate the WWDG timeout.
When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.

Figure 272. Window watchdog timing diagram

Refresh not allowed
t WWDG = t PCLK
: WWDG timeout
: APB clock period measured in ms
Refresh allowed
0x41
0x40
0x3F
WDGTB[2:0]
× ×
4096 2
RM0453 Rev 1
WDGTB
T x 4096 x 2
pclk
EWIF = 0
× ( [ ] ) (
T 5:0 + 1
RM0453
Time
MS47266V1
)
ms