Dac Register Map; Table 59. Dac Register Map - ST STM32F40 Series Reference Manual

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Digital-to-analog converter (DAC)

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DMAUDR2: DAC channel2 DMA underrun flag

This bit is set by hardware and cleared by software (by writing it to 1).

0: No DMA underrun error condition occurred for DAC channel2

1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is

driving DAC channel2 conversion at a frequency higher than the DMA service capability rate)

Bits 28:14 Reserved, must be kept at reset value.

Bit 13 DMAUDR1: DAC channel1 DMA underrun flag

This bit is set by hardware and cleared by software (by writing it to 1).

0: No DMA underrun error condition occurred for DAC channel1

1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is

driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bits 12:0 Reserved, must be kept at reset value.

DAC register map

DAC register map

summarizes the DAC registers.

DACC2DHR[11:0]

Table 2 on page 52

for the register boundary addresses.

Doc ID 018909 Rev 4

DACC1DHR[11:0]

DACC1DHR[7:0]

DACC2DHR[11:0]

DACC2DHR[7:0]

DACC1DHR[11:0]

DACC2DHR[7:0]

DACC1DHR[7:0]

DACC1DOR[11:0]

DACC2DOR[11:0]

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