ST STM32F40 Series Reference Manual page 926

RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
been transferred. Upon completion of the EOF frame transfer, the status word is popped out
and sent to the DMA controller.
In Rx FIFO Store-and-forward mode (configured by the RSF bit in the ETH_DMAOMR
register), a frame is read out only after being written completely into the Receive FIFO. In
this mode, all error frames are dropped (if the core is configured to do so) such that only
valid frames are read out and forwarded to the application. In Cut-through mode, some error
frames are not dropped, because the error status is received at the end of the frame, by
which time the start of that frame has already been read out of the FIFO.
A receive operation is initiated when the MAC detects an SFD on the MII. The core strips the
preamble and SFD before proceeding to process the frame. The header fields are checked
for the filtering and the FCS field used to verify the CRC for the frame. The frame is dropped
in the core if it fails the address filter.
Receive protocol
The received frame preamble and SFD are stripped. Once the SFD has been detected, the
MAC starts sending the Ethernet frame data to the receive FIFO, beginning with the first
byte following the SFD (destination address). If IEEE 1588 time stamping is enabled, a
snapshot of the system time is taken when any frame's SFD is detected on the MII. Unless
the MAC filters out and drops the frame, this time stamp is passed on to the application.
If the received frame length/type field is less than 0x600 and if the MAC is programmed for
the auto CRC/pad stripping option, the MAC sends the data of the frame to RxFIFO up to
the count specified in the length/type field, then starts dropping bytes (including the FCS
field). If the Length/Type field is greater than or equal to 0x600, the MAC sends all received
Ethernet frame data to Rx FIFO, regardless of the value on the programmed auto-CRC strip
option. The MAC watchdog timer is enabled by default, that is, frames above 2048 bytes (DA
+ SA + LT + Data + pad + FCS) are cut off. This feature can be disabled by programming the
watchdog disable (WD) bit in the MAC configuration register. However, even if the watchdog
timer is disabled, frames greater than 16 KB in size are cut off and a watchdog timeout
status is given.
Receive CRC: automatic CRC and pad stripping
The MAC checks for any CRC error in the receiving frame. It calculates the 32-bit CRC for
the received frame that includes the Destination address field through the FCS field. The
encoding is defined by the following polynomial.
32 26 23 22 16 12 11 10 8 7 5 4 2
G x ( )
x x x x x x x x x x x x x x 1
= + + + + + + + + + + + + + +
Regardless of the auto-pad/CRC strip, the MAC receives the entire frame to compute the
CRC check for the received frame.
Receive checksum offload
Both IPv4 and IPv6 frames in the received Ethernet frames are detected and processed for
data integrity. You can enable the receive checksum offload by setting the IPCO bit in the
ETH_MACCR register. The MAC receiver identifies IPv4 or IPv6 frames by checking for
value 0x0800 or 0x86DD, respectively, in the received Ethernet frame Type field. This
identification applies to VLAN-tagged frames as well. The receive checksum offload
calculates IPv4 header checksums and checks that they match the received IPv4 header
checksums. The IP Header Error bit is set for any mismatch between the indicated payload
Doc ID 018909 Rev 4 926/1422