Rcc Apb1 Peripheral Clock Enable Register For Stm32F42Xxx And Stm32F43Xxx(Rcc_Apb1Enr) - ST STM32F40 Series Reference Manual

Reset and clock control for (RCC)
Bit 2 TIM4EN: TIM4 clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
6.3.16 RCC APB1 peripheral clock enable register
for STM32F42xxx and STM32F43xxx(RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
DAC PWR
UART8 UART7
EN EN
EN
rw rw rw
15 14 13
SPI3 SPI2
EN EN
Reserved
rw rw
Bits 31 UART8EN: UART8 clock enable
Set and cleared by software.
0: UART8 clock disabled
1: UART8 clock enabled
Bits 30 UART7EN: UART7 clock enable
Set and cleared by software.
0: UART7 clock disabled
1: UART7 clock enabled
Bit 29 DACEN: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 Reserved, must be kept at reset value.
151/1422
28 27 26 25
CAN2 CAN1
Reser-
EN EN EN
ved
rw rw rw
12 11 10 9
WWDG
EN
Reserved
rw
Doc ID 018909 Rev 4
24 23 22 21
I2C3 I2C2 I2C1
Reser-
EN EN EN
ved
rw rw rw
8 7 6 5
TIM14 TIM13 TIM12 TIM7
EN EN EN EN
rw rw rw rw
20 19 18
UART5 UART4 USART3 USART2
EN EN EN
rw rw rw
4 3 2
TIM6 TIM5 TIM4 TIM3
EN EN EN
rw rw rw
RM0090
17 16
Reser-
EN
ved
rw
1 0
TIM2
EN EN
rw rw