ST STM32F40 Series Reference Manual page 993

Ethernet (ETH): media access control (MAC) with DMA controller
Bit 15 TGFMSCS: Transmitted good frames more single collision status
Bit 14 TGFSCS: Transmitted good frames single collision status
Bits 13:0 Reserved, must be kept at reset value.
Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
Address offset: 0x010C
Reset value: 0x0000 0000
The Ethernet MMC receive interrupt mask register maintains the masks for interrupts
generated when the receive statistic counters reach half their maximum value. (MSB of the
counter is set.) It is a 32-bit wide register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Reserved
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 RGUFM: Received good unicast frames mask
Bits 16:7 Reserved, must be kept at reset value.
Bit 6 RFAEM: Received frames alignment error mask
Bit 5 RFCEM: Received frame CRC error mask
Bits 4:0 Reserved, must be kept at reset value.
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This bit is set when the transmitted, good frames after more than a single collision, counter
reaches half the maximum value.
This bit is set when the transmitted, good frames after a single collision, counter reaches half
the maximum value.
Setting this bit masks the interrupt when the received, good unicast frames, counter reaches
half the maximum value.
Setting this bit masks the interrupt when the received frames, with alignment error, counter
reaches half the maximum value.
Setting this bit masks the interrupt when the received frames, with CRC error, counter
reaches half the maximum value.
Doc ID 018909 Rev 4
17 16 15 14 13 12 11 10
Reserved
rw
9 8 7 6 5 4 3
Reserved
rw rw
RM0090
2 1 0