Dma Transactions; Figure 26. System Implementation Of The Two Dma Controllers (Stm32F42Xxx And Stm32F43Xxx) - ST STM32F40 Series Reference Manual

DMA controller (DMA)
Figure 26. System implementation of the two DMA controllers (STM32F42xxx and
STM32F43xxx)
DMA controller 2
DMA controller 1
1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus
only DMA2 streams are able to perform memory-to-memory transfers.
9.3.2

DMA transactions

A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-
programmable.
Each DMA transfer consists of three operations:
● A loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
●
A storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
●
A post-decrement of the DMA_SxNDTR register, which contains the number of
transactions that still have to be performed
217/1422
DMA request
MAPPING
Doc ID 018909 Rev 4
Bus Matrix
DCODE
(AHB multilayer)
ICODE
AHB-APB
bridge2
(dual AHB)
AHB-APB
bridge1
(dual AHB)
RM0090
Flash
memory
112 KB SRAM
16 KB SRAM
64 KB SRAM
AHB1 peripherals
APB2
APB2
peripherals
APB1
APB1
peripherals
AHB2 peripherals
External memory
controller (FSMC)
MS30437V1