Spi Control Register 2 (Spi_Cr2) - ST STM32F40 Series Reference Manual

Serial peripheral interface (SPI)
Bit 0 CPHA: Clock phase
Note: This bit should not be changed when communication is ongoing.
Note: Not used in I
27.5.2

SPI control register 2 (SPI_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 TXEIE: Tx buffer empty interrupt enable
Bit 6 RXNEIE: RX buffer not empty interrupt enable
Bit 5 ERRIE: Error interrupt enable
Bit 4 FRF: Frame format
Note: Not used in I
Bit 3 Reserved. Forced to 0 by hardware.
Bit 2 SSOE: SS output enable
Note: Not used in I
Bit 1 TXDMAEN: Tx buffer DMA enable
Bit 0 RXDMAEN: Rx buffer DMA enable
839/1422
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
2
S mode and SPI TI mode
11 10 9
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is
set.
This bit controls the generation of an interrupt when an error condition occurs (CRCERR,
OVR, MODF in SPI mode and UDR, OVR and FRE).
0: Error interrupt is masked
1: Error interrupt is enabled
0: SPI Motorola mode
1 SPI TI mode
2
S mode
0: SS output is disabled in master mode and the cell can work in multimaster configuration
1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work
in a multimaster environment.
2
S mode and SPI TI mode
When this bit is set, the DMA request is made whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
When this bit is set, the DMA request is made whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled
Doc ID 018909 Rev 4
8 7 6 5
TXEIE RXNEIE ERRIE
rw rw rw
4 3 2 1
FRF SSOE TXDMAEN RXDMAEN
Res.
rw rw rw
RM0090
0
rw