Forced Output Mode; Figure 147. Pwm Input Mode Timing - ST STM32F40 Series Reference Manual

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For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in

TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending

on CK_INT frequency and prescaler value):

Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1

Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter

clear): write the CC1P to '0' and the CC1NP bit to '0' (active on rising edge).

Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1

Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P

bit to '1' and the CC2NP bit to '0'(active on falling edge).

Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register

(TI1FP1 selected).

Configure the slave mode controller in reset mode: write the SMS bits to 100 in the

TIMx_SMCR register.

Enable the captures: write the CC1E and CC2E bits to '1 in the TIMx_CCER register.

Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx) can be forced to active or inactive level directly by software,

independently of any comparison between the output compare register and the counter.

To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101

in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high

(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.

ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx

reset counter

Doc ID 018909 Rev 4

General-purpose timers (TIM2 to TIM5)

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