Rcc Apb1 Peripheral Clock Enable In Low Power Mode Register For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx (Rcc_Apb1Lpenr) - ST STM32F40 Series Reference Manual

Reset and clock control for (RCC)
6.3.23 RCC APB1 peripheral clock enable in low power mode register
for STM32F405xx/07xx and STM32F415xx/17xx
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0x36FE C9FF
Access: no wait state, word, half-word and byte access.
31 30 29
DAC PWR
LPEN LPEN
Reserved
rw
15 14 13
SPI3 SPI2
LPEN LPEN
Reserved
rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACLPEN: DAC interface clock enable during Sleep mode
Set and cleared by software.
0: DAC interface clock disabled during Sleep mode
1: DAC interface clock enabled during Sleep mode
Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Power interface clock disabled during Sleep mode
1: Power interface clock enabled during Sleep mode
Bit 27 Reserved, must be kept at reset value.
Bit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode
Set and cleared by software.
0: CAN 2 clock disabled during sleep mode
1: CAN 2 clock enabled during sleep mode
Bit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode
Set and cleared by software.
0: CAN 1 clock disabled during Sleep mode
1: CAN 1 clock enabled during Sleep mode
Bit 24 Reserved, must be kept at reset value.
Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode
Set and cleared by software.
0: I2C3 clock disabled during Sleep mode
1: I2C3 clock enabled during Sleep mode
Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode
Set and cleared by software.
0: I2C2 clock disabled during Sleep mode
1: I2C2 clock enabled during Sleep mode
165/1422
28 27 26 25
CAN2 CAN1
RESER
VED
LPEN LPEN
rw rw rw
12 11 10 9
WWDG
LPEN
Reserved
rw
Doc ID 018909 Rev 4
24 23 22 21
I2C3 I2C2 I2C1
Reser-
LPEN LPEN LPEN
ved
rw rw rw
8 7 6 5
TIM14 TIM13 TIM12 TIM7
LPEN LPEN LPEN LPEN
rw rw rw rw
20 19 18
UART5 UART4 USART3 USART2
LPEN LPEN LPEN LPEN
rw rw rw
4 3 2
TIM6 TIM5 TIM4 TIM3
LPEN LPEN LPEN LPEN
rw rw rw
RM0090
17 16
Reser-
ved
rw
1 0
TIM2
LPEN
rw rw