Pwr Power Control Register (Pwr_Cr); For Stm32F42Xxx And Stm32F43Xxx - ST STM32F40 Series Reference Manual

RM0090
Bit 4 PVDE: Power voltage detector enable
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
Bit 0 LPDS: Low-power deepsleep
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
5.4.2

PWR power control register (PWR_CR)

STM32F42xxx and STM32F43xxx
for
Address offset: 0x00
Reset value: 0x0000 C000 (reset by wakeup from Standby mode)
31 30 29
15 14 13
VOS ADCDC1
rw rw rw
28 27 26 25
12 11 10 9
FPDS
Reserved
rw
Doc ID 018909 Rev 4
24 23 22 21
Reserved
8 7 6 5
DBP PLS[2:0]
rw rw rw rw
Power controller (PWR)
20 19 18 17
4 3 2 1
PVDE CSBF CWUF PDDS
rw rc_w1 rc_w1 rw
16
0
LPDS
rw
106/1422