Timx Counter (Timx_Cnt); Timx Prescaler (Timx_Psc); Timx Auto-Reload Register (Timx_Arr) - ST STM32F40 Series Reference Manual

RM0090
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
15.4.10

TIMx counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000
15 14 13
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Bits 15:0 CNT[15:0]: Counter value
15.4.11

TIMx prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler value
15.4.12

TIMx auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0x0000
15 14 13
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Bits 15:0
12 11 10 9
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12 11 10 9
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The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event.
12 11 10 9
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ARR[15:0]: Auto-reloadvalue
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 15.3.1: Time-base unit on page 423
and behavior.
The counter is blocked while the auto-reload value is null.
Doc ID 018909 Rev 4
General-purpose timers (TIM2 to TIM5)
8 7 6 5
CNT[15:0]
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8 7 6 5
PSC[15:0]
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CK_PSC
8 7 6 5
ARR[15:0]
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4 3 2
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4 3 2
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/ (PSC[15:0] + 1).
4 3 2
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for more details about ARR update
1 0
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1 0
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1 0
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