ST STM32F40 Series Reference Manual page 1019

Ethernet (ETH): media access control (MAC) with DMA controller
Table 170. Ethernet register map and reset values (continued)
Offset Register
ETH_MMCTG
FCR
0x168
Reset value 0 0
ETH_MMCRF
CECR
0x194
Reset value 0 0
ETH_MMCRF
AECR
0x198
Reset value 0 0
ETH_MMCR
GUFCR
0x1C4
Reset value 0 0
ETH_PTPTS
CR
0x700
Reset value
ETH_PTPSSI
R
0x704
Reset value
ETH_PTPTS
HR
0x708
Reset value 0 0
ETH_PTPTSL
R
0x70C
Reset value 0 0
ETH_PTPTS
HUR
0x710
Reset value 0 0
ETH_PTPTSL
UR
0x714
Reset value 0 0
ETH_PTPTS
AR
0x718
Reset value 0 0
ETH_PTPTT
HR
0x71C
Reset value 0 0
ETH_PTPTTL
R
0x720
Reset value 0 0
ETH_PTPTS
SR
0x728
Reset value
ETH_DMABM
0x1000 R Reserved
Reset value
ETH_DMATP
DR
0x1004
Reset value 0 0
ETH_DMARP
DR
0x1008
Reset value 0 0
ETH_DMARD
LAR
0x100C
Reset value 0 0
ETH_DMATD
LAR
0x1010
Reset value 0 0
ETH_DMASR
0x1014
Reset value
1019/1422
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
Doc ID 018909 Rev 4
TGFC
0 0 0 0 0 0 0 0
RFCEC
0 0 0 0 0 0 0 0
RFAEC
0 0 0 0 0 0 0 0
RGUFC
0 0 0 0 0 0 0 0
0 0 0 0 0
Reserved
STS[31:0]
0 0 0 0 0 0 0 0
STSS
0 0 0 0 0 0 0 0
TSUS
0 0 0 0 0 0 0 0
TSUSS
0 0 0 0 0 0 0 0
TSA
0 0 0 0 0 0 0 0
TTSH
0 0 0 0 0 0 0 0
TTSL
0 0 0 0 0 0 0 0
Reserved
RDP PM
0 0 0 0 1 0 0 0
TPD
0 0 0 0 0 0 0 0
RPD
0 0 0 0 0 0 0 0
SRL
0 0 0 0 0 0 0 0
STL
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PBL
0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0
RM0090
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
STSSI
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0
DSL
0 0 0 0 0 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0