ST STM32F40 Series Reference Manual page 692

RM0090
Bit 4 FMPIE1
Bit 3 FOVIE0
Bit 2 FFIE0
Bit 1 FMPIE0
Bit 0 TMEIE
Note: Refer to
CAN error status register (CAN_ESR)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
r r r
15 14 13
Bits 31:24 REC[7:0]
Bits 23:16 TEC[7:0]
Bits 15:7 Reserved, must be kept at reset value.
:
FIFO message pending interrupt enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
:
FIFO overrun interrupt enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
:
FIFO full interrupt enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
:
FIFO message pending interrupt enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
:
Transmit mailbox empty interrupt enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
Section 24.8: bxCAN
28 27 26 25
REC[7:0]
r r r r
12 11 10 9
Reserved
:
Receive error counter
The implementing part of the fault confinement mechanism of the CAN protocol. In case of
an error during reception, this counter is incremented by 1 or by 8 depending on the error
condition as defined by the CAN standard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was higher than 128. When the counter value
exceeds 127, the CAN controller enters the error passive state.
:
Least significant byte of the 9-bit transmit error counter
The implementing part of the fault confinement mechanism of the CAN protocol.
Doc ID 018909 Rev 4
Controller area network (bxCAN)
interrupts.
24 23 22 21
r r r r
8 7 6 5
LEC[2:0]
rw rw
20 19 18 17
TEC[7:0]
r r r r
4 3 2 1
BOFF EPVF
Res.
rw r r
16
r
0
EWGF
r
692/1422