Figure 171. Counter Timing Diagram, Internal Clock Divided By 4; Figure 172. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F40 Series Reference Manual

RM0090

Figure 171. Counter timing diagram, internal clock divided by 4

Figure 172. Counter timing diagram, internal clock divided by N

Figure 173. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
Doc ID 018909 Rev 4
General-purpose timers (TIM9 to TIM14)
0035
0036
1F 20
31 32 33 34 35 36 00 01 02 03 04 05 06 07
FF
0000 0001
00
36
488/1422