Hash Data Input Register (Hash_Din) - ST STM32F40 Series Reference Manual

Hash processor (HASH)
22.4.3

HASH data input register (HASH_DIN)

Address offset: 0x04
Reset value: 0x0000 0000
HASH_DIN is the data input register. It is 32-bit wide. It is used to enter the message by
blocks of 512 bits. When the HASH_DIN register is written to, the value presented on the
AHB databus is 'pushed' into the HASH core and the register takes the new value presented
on the AHB databus. The DATATYPE bits must previously have been configured in the
HASH_CR register to get a correct message representation.
When a block of 16 words has been written to the HASH_DIN register, an intermediate
digest calculation is launched:
● by writing new data into the HASH_DIN register (the first word of the next block) if the
DMA is not used (intermediate digest calculation)
●
automatically if the DMA is used
When the last block has been written to the HASH_DIN register, the final digest calculation
(including padding) is launched:
●
by writing the DCAL bit to 1 in the HASH_STR register (final digest calculation)
●
automatically if the DMA is used and MDMAT bit is set to '0'.
When a digest calculation (intermediate or final) is in progress, any new write access to the
HASH_DIN register is extended (by wait-state insertion on the AHB bus) until the HASH
calculation completes.
When the HASH_DIN register is read, the last word written in this location is accessed (zero
after reset).
.
31 30 29
rw rw rw
15 14 13
rw rw rw
615/1422
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Bit 31:0 DATAIN: Data input
Read = returns the current register content.
Write = the current register content is pushed into the IN FIFO, and the register
takes the new value presented on the AHB databus.
Doc ID 018909 Rev 4
24 23 22 21
DATAIN
rw rw rw rw
8 7 6 5
DATAIN
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0090
16
rw
0
rw