ST STM32F40 Series Reference Manual page 989

Ethernet (ETH): media access control (MAC) with DMA controller
Bits 23:16Reserved, must be kept at reset value.
MACA2H: MAC address2 high [47:32]
Bits 15:0
Ethernet MAC address 2 low register (ETH_MACA2LR)
Address offset: 0x0054
Reset value: 0xFFFF FFFF
The MAC address 2 low register holds the lower 32 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MACA2L: MAC address2 low [31:0]
Ethernet MAC address 3 high register (ETH_MACA3HR)
Address offset: 0x0058
Reset value: 0x0000 FFFF
The MAC address 3 high register holds the upper 16 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AE SA MBC
rw rw rw rw rw rw rw rw
Bit 31 AE: Address enable
When this bit is set, the address filters use the MAC address3 for perfect filtering. When this
bit is cleared, the address filters ignore the address for filtering.
Bit 30 SA: Source address
When this bit is set, the MAC address 3 [47:0] is used for comparison with the SA fields of the
received frame.
When this bit is cleared, the MAC address 3[47:0] is used for comparison with the DA fields of
the received frame.
989/1422
This field contains the upper 16 bits (47:32) of the 6-byte MAC address2.
This field contains the lower 32 bits of the 6-byte second MAC address2. The content of this
field is undefined until loaded by the application after the initialization process.
Reserved
Doc ID 018909 Rev 4
MACA2L
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
9 8 7 6 5 4 3
9 8 7 6 5 4 3
MACA3H
RM0090
2 1 0
2 1 0