Figure 238. I2C Bus Protocol; Figure 239. I2C Block Diagram For Stm32F40X/41X - ST STM32F40 Series Reference Manual

RM0090
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to
Figure 238. I
Acknowledge may be enabled or disabled by software. The I
addressing 7-bit/ 10-bit and/or general call address) can be selected by software.
The block diagram of the I
Figure 239. I
SDA
SCL
SMBA
2
C bus protocol
SDA
MSB
SCL
1
Start
condition
2
C interface is shown in
2
C block diagram for STM32F40x/41x
Data
control
Clock
control
Clock control
Register (CCR)
Control registers
(CR1&CR2)
Status registers
(SR1&SR2)
Doc ID 018909 Rev 4
Inter-integrated circuit (I
Figure 238.
2 8
2
C interface addresses (dual
Figure 239.
Data register
Data shift register
Comparator
Own address register
Dual address register
PEC register
Control
logic
Interrupts
2
C) interface
ACK
9
Stop
condition
PEC calculation
DMA requests & ACK
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