Cryp Key Registers (Cryp_K0 - ST STM32F40 Series Reference Manual

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CRYP key registers (CRYP_K0...3(L/R)R)

Address offset: 0x20 to 0x3C

Reset value: 0x0000 0000

These registers contain the cryptographic keys.

In the TDES mode, keys are 64-bit binary values (number from left to right, that is the

leftmost bit is bit 1), named K1, K2 and K3 (K0 is not used), each key consists of 56

information bits and 8 parity bits. The parity bits are reserved for error detection purposes

and are not used by the current block. Thus, bits 8, 16, 24, 32, 40, 48, 56 and 64 of each 64-

bit key value Kx[1:64] are not used.

In the AES mode, the key is considered as a single 128-, 192- or 256-bit long bit sequence,

for AES-128: k

for AES-192: k

for AES-256: k

In any case b

CRYP_K0LR (address offset: 0x20)

CRYP_K0RR (address offset: 0x24)

CRYP_K1LR (address offset: 0x28)

Bit 0 INMIS: Input FIFO service masked interrupt status

Gives the interrupt state after masking of the input FIFO service interrupt.

0: Interrupt not pending

1: Interrupt pending when CRYPEN = 1

being the leftmost bit). The AES key is entered into the registers as

corresponds to b

corresponds to b

corresponds to b

is the rightmost bit.

Doc ID 018909 Rev 4

Cryptographic processor (CRYP)

are not used),

are not used),

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