Dma Functional Description; General Description; Figure 24. Dma Block Diagram - ST STM32F40 Series Reference Manual

DMA controller (DMA)
9.3

DMA functional description

9.3.1

General description

Figure 24

Figure 24. DMA block diagram

DMA controller
REQ_STR0_CH0
REQ_STR0_CH1
REQ_STR0_CH7
REQ_STR1_CH0
REQ_STR1_CH1
REQ_STR1_CH7
REQ_STR7_CH0
REQ_STR7_CH1
REQ_STR7_CH7
The DMA controller performs direct memory transfer: as an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
It can carry out the following transactions:
●
peripheral-to-memory
●
memory-to-peripheral
●
memory-to-memory
The DMA controller provides two AHB master ports: the AHB memory port, intended to be
connected to memories and the AHB peripheral port, intended to be connected to
peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must
also have access to the memories.
The AHB slave port is used to program the DMA controller (it supports only 32-bit
accesses).
See Figure 25
215/1422
shows the block diagram of a DMA.
REQ_STREAM0
REQ_STREAM1
REQ_STREAM2
REQ_STREAM3
REQ_STREAM4
REQ_STREAM5
REQ_STREAM6
REQ_STREAM7
Channel
selection
and Figure 26 for the implementation of the system of two DMA controllers.
Doc ID 018909 Rev 4
Arbiter
Memory port
Peripheral port
AHB slave
Programming port
programming
interface
RM0090
ai15945