Clock Source; Debug Mode - ST STM32F40 Series Reference Manual

RM0090
Figure 196. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
17.3.3

Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 197
without prescaler.
Figure 197. Control circuit in normal mode, internal clock divided by 1
Counter clock = CK_CNT = CK_PSC
17.3.4

Debug mode

When the microcontroller enters the debug mode (Cortex™-M4F core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to
support for timers, watchdog, bxCAN and
preloaded)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Write a new value in TIMx_ARR
shows the behavior of the control circuit and the upcounter in normal mode,
CK_INT
CEN=CNT_EN
UG
CNT_INIT
Counter register
Doc ID 018909 Rev 4
F0 F1 F2 F3 F4 F5
F5
F5
31 32 33 34 35 36 00 01 02 03 04 05 06 07
I2C.
Basic timers (TIM6&TIM7)
00 01 02 03 04 05 06 07
36
36
Section 33.16.2: Debug
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