Rtc Write Protection Register (Rtc_Wpr); Rtc Sub Second Register (Rtc_Ssr) - ST STM32F40 Series Reference Manual

Real-time clock (RTC)
23.6.10

RTC write protection register (RTC_WPR)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY: Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to
protection.
23.6.11

RTC sub second register (RTC_SSR)

Address offset: 0x28
Power-on reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31 30 29
r r r
15 14 13
r r r
Bits31:16 Reserved
Bits 15:0 SS: Sub second value
SS[15:0] is the value in the synchronous prescaler's counter. The fraction of a second is
given by the formula below:
Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 )
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
653/1422
28 27 26 25
12 11 10 9
Reserved
RTC register write protection
28 27 26 25
r r r r
12 11 10 9
r r r r
time/date is one second less than as indicated by RTC_TR/RTC_DR.
Doc ID 018909 Rev 4
24 23 22 21
Reserved
8 7 6 5
w w w
for a description of how to unlock RTC register write
24 23 22 21
Reserved
r r r r
8 7 6 5
SS[15:0]
r r r r
20 19 18 17
4 3 2 1
KEY
w w w w
20 19 18 17
r r r r
4 3 2 1
r r r r
RM0090
16
0
w
16
r
0
r