Hash Interrupt Enable Register (Hash_Imr) - ST STM32F40 Series Reference Manual

Hash processor (HASH)
HASH_HR6
Address offset: 0x328
31 30 29
r r r
15 14 13
r r r
HASH_HR7
Address offset: 0x32C
31 30 29
r r r
15 14 13
r r r
Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these
registers assume their reset values.
22.4.6

HASH interrupt enable register (HASH_IMR)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
15 14 13
619/1422
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
12 11 10 9
Reserved
Bits 31:2 Reserved, forced by hardware to 0.
Bit 1 DCIE: Digest calculation completion interrupt enable
0: Digest calculation completion interrupt disabled
1: Digest calculation completion interrupt enabled.
Bit 0 DINIE: Data input interrupt enable
0: Data input interrupt disabled
1: Data input interrupt enabled
Doc ID 018909 Rev 4
24 23 22 21
H6
r r r r
8 7 6 5
H6
r r r r
24 23 22 21
H7
r r r r
8 7 6 5
H7
r r r r
24 23 22 21
Reserved
8 7 6 5
20 19 18 17
r r r r
4 3 2 1
r r r r
20 19 18 17
r r r r
4 3 2 1
r r r r
20 19 18 17
4 3 2 1
DCIE
rw
RM0090
16
r
0
r
16
r
0
r
16
0
DINIE
rw