Dac Channel1 Data Output Register (Dac_Dor1); Dac Channel2 Data Output Register (Dac_Dor2); Dac Status Register (Dac_Sr) - ST STM32F40 Series Reference Manual

RM0090
12.5.12

DAC channel1 data output register (DAC_DOR1)

Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
12.5.13

DAC channel2 data output register (DAC_DOR2)

Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bit 11:0 DACC2DOR[11:0]: DAC channel2 data output
12.5.14

DAC status register (DAC_SR)

Address offset: 0x34
Reset value: 0x0000 0000
31 30 29
DMAUDR2
Reserved
rc_w1
15 14 13
DMAUDR1
Reserved
rc_w1
27 26 25
11 10 9
r r r
27 26 25
11 10 9
r r r
These bits are read-only, they contain data output for DAC channel2.
28 27 26 25
12 11 10
Doc ID 018909 Rev 4
24 23 22
Reserved
8 7 6
DACC1DOR[11:0]
r r r
24 23 22
Reserved
8 7 6
DACC2DOR[11:0]
r r r
24 23 22
Reserved
9 8 7 6
Reserved
Digital-to-analog converter (DAC)
21 20 19 18
5 4 3 2
r r r r
21 20 19 18
5 4 3 2
r r r r
21 20 19 18
5 4 3 2
17 16
1 0
r r
17 16
1 0
r r
17 16
1 0
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