Adc Regular Sequence Register 3 (Adc_Sqr3); Adc Injected Sequence Register (Adc_Jsqr) - ST STM32F40 Series Reference Manual

RM0090
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence

11.13.11 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x34
Reset value: 0x0000 0000
31 30 29 28
Reserved
rw rw
15 14 13 12
SQ4_0 SQ3[4:0]
rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence

11.13.12 ADC injected sequence register (ADC_JSQR)

Address offset: 0x38
Reset value: 0x0000 0000
31 30 29
15 14 13
JSQ4[0] JSQ3[4:0]
rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 JL[1:0]: Injected sequence length
27 26 25
SQ6[4:0]
rw rw rw
11 10 9
rw rw rw
These bits are written by software with the channel number (0..18) assigned as the 6th in the
sequence to be converted.
28 27 26 25
Reserved
12 11 10 9
rw rw rw rw
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Doc ID 018909 Rev 4
Analog-to-digital converter (ADC)
24 23 22 21
SQ5[4:0]
rw rw rw rw
8 7 6 5
SQ2[4:0]
rw rw rw rw
24 23 22 21
rw
8 7 6 5
JSQ2[4:0]
rw rw rw rw
20 19 18
SQ4[4:1]
rw rw rw
4 3 2
SQ1[4:0]
rw rw rw
20 19 18
JL[1:0] JSQ4[4:1]
rw rw rw
4 3 2
JSQ1[4:0]
rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
300/1422