ST STM32F40 Series Reference Manual page 995

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MMC transmitted good frames after more than a single collision
counter register (ETH_MMCTGFMSCCR)
Address offset: 0x0150
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after more than a
single collision in Half-duplex mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
Address offset: 0x0168
Reset value: 0x0000 0000
This register contains the number of good frames transmitted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 TGFC: Transmitted good frames counter
Ethernet MMC received frames with CRC error counter register
(ETH_MMCRFCECR)
Address offset: 0x0194
Reset value: 0x0000 0000
This register contains the number of frames received with CRC error.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
995/1422
r r r r r r
Bits 31:0 TGFMSCC: Transmitted good frames more single collision counter
Transmitted good frames after more than a single collision counter
r r r r r r
r r r r r r
Bits 31:0 RFCEC: Received frames CRC error counter
Received frames with CRC error counter
Doc ID 018909 Rev 4
TGFMSCC
r r r r r r r
TGFC
r r r r r r r
RFCEC
r r r r r r r
9 8 7 6 5
r r r r r r r
9 8 7 6 5
r r r r r r r
9 8 7 6 5
r r r r r r r
RM0090
4 3 2 1 0
r r r r r
4 3 2 1 0
r r r r r
4 3 2 1 0
r r r r r