ST STM32F42 Series Microcontroller Manuals
Manuals and User Guides for ST STM32F42 Series Microcontroller. We have 1 ST STM32F42 Series Microcontroller manual available for free PDF download: Reference Manual
ST STM32F42 Series Reference Manual (1422 pages)
Brand: ST
|
Category: Microcontrollers
|
Size: 15 MB
Table of Contents
-
Glossary48
-
S0: I-Bus51
-
S1: D-Bus51
-
S2: S-Bus51
-
Busmatrix51
-
Memory Map52
-
Bit Banding55
-
Introduction59
-
Erase66
-
Programming67
-
Interrupts68
-
Option Bytes68
-
Sleep Mode98
-
Stop Mode99
-
Standby Mode101
-
PWR Register Map109
-
Reset111
-
System Reset111
-
Power Reset112
-
Clocks113
-
HSE Clock116
-
HSI Clock117
-
LSE Clock118
-
LSI Clock118
-
RTC/AWU Clock119
-
Watchdog Clock120
-
RCC Registers123
-
RCC Register Map181
-
Port Pins196
-
GPIO Registers198
-
(X = a199
-
(X = a201
-
(X = a203
-
SYSCFG Registers206
-
(Syscfg_Exticr1)208
-
(Syscfg_Exticr2)209
-
(Syscfg_Exticr3)209
-
(Syscfg_Exticr4)210
-
DMA Introduction213
-
DMA Transactions217
-
Arbiter219
-
DMA Streams220
-
Circular Mode224
-
Fifo227
-
Flow Controller231
-
Error Management234
-
DMA Interrupts235
-
DMA Registers235
-
DMA Register Map245
-
NVIC Features249
-
EXTI Registers260
-
ADC Introduction264
-
ADC Clock266
-
Timing Diagram268
-
Analog Watchdog268
-
Scan Mode269
-
Data Alignment272
-
Data Management276
-
Using the DMA276
-
Multi ADC Mode277
-
Interleaved Mode283
-
ADC Interrupts290
-
ADC Registers291
-
(Adc_Cdr)307
-
DAC Introduction310
-
DAC Data Format312
-
DAC Conversion313
-
DMA Request314
-
Noise Generation315
-
DAC Registers321
-
(Dac_Dhr12R1)324
-
(Dac_Dhr12L1)325
-
(Dac_Dhr8R1)325
-
(Dac_Dhr12R2)325
-
(Dac_Dhr12L2)326
-
(Dac_Dhr8R2)326
-
(Dac_Dhr12Ld)327
-
(Dac_Dhr8Rd)327
-
DAC Register Map329
-
DCMI Pins330
-
DCMI Clocks330
-
DMA Interface332
-
Synchronization334
-
Capture Modes336
-
Crop Feature337
-
JPEG Format338
-
Fifo338
-
Data Formats339
-
RGB Format339
-
Ycbcr Format340
-
DCMI Interrupts340
-
Time-Base Unit356
-
Counter Modes357
-
Clock Selection367
-
PWM Input Mode372
-
PWM Mode375
-
One-Pulse Mode384
-
Debug Mode393
-
Time-Base Unit423
-
Counter Modes425
-
Clock Selection434
-
PWM Input Mode439
-
PWM Mode442
-
One-Pulse Mode445
-
Debug Mode458
-
Time-Base Unit485
-
Counter Modes486
-
Clock Selection489
-
PWM Mode496
-
One-Pulse Mode497
-
Debug Mode501
-
(Timx_Ccmr1)519
-
(Timx_Ccer)521
-
Time-Base Unit526
-
Counting Mode527
-
Clock Source530
-
Debug Mode530
-
Debug Mode537
-
IWDG Registers537
-
Debug Mode544
-
WWDG Registers545
-
Data Type567
-
CRYP Busy State571
-
Context Swapping573
-
CRYP Interrupts575
-
CRYP Registers576
-
RNG Introduction594
-
Operation595
-
Error Management595
-
RNG Registers595
-
RNG Register Map598
-
Data Type602
-
Message Padding605
-
Hash Operation606
-
HMAC Operation606
-
Context Swapping607
-
HASH Interrupt609
-
HASH Registers609
-
Introduction625
-
Tamper Detection638
-
Alarm Output640
-
RTC Interrupts640
-
RTC Registers642
-
(Rtc_Tafcr)658
-
RTC Register Map662
-
Tx Mailboxes666
-
Normal Mode668
-
Test Mode669
-
Silent Mode669
-
Loop Back Mode670
-
Debug Mode671
-
Message Storage678
-
Error Management680
-
Bit Timing680
-
Bxcan Interrupts683
-
CAN Registers684
-
Mode Selection709
-
I2C Slave Mode711
-
I2C Master Mode714
-
Error Conditions719
-
Smbus721
-
DMA Requests724
-
I 2 C Interrupts726
-
I 2 C Debug Mode728
-
I 2 C Registers728
-
I2C Register Map741
-
Transmitter747
-
Receiver750
-
Parity Control767
-
Smartcard773
-
USART Interrupts781
-
USART Registers782
-
SPI Introduction794
-
SPI Features795
-
I 2 S Features796
-
CRC Calculation812
-
Status Flags814
-
Error Flags818
-
SPI Interrupts819
-
I2S Full Duplex821
-
Clock Generator828
-
I 2 S Slave Mode832
-
Status Flags834
-
Error Flags835
-
I 2 S Interrupts836
-
DMA Features836
-
Table 126. I836
-
Mode)841
-
Mode)842
-
SPI Register Map845
-
SDIO Adapter850
-
Card Reset861
-
Block Write863
-
Block Read863
-
SD I/O Mode876
-
Response Formats880
-
R1B881
-
R4 (Fast I/O)882
-
R4B882
-
SDIO Interrupts885
-
CE-ATA Interrupt886
-
Aborting CMD61886
-
HW Flow Control886
-
SDIO Registers887
-
SDIO Response 1891
-
DMA Features905
-
PTP Features905
-
Ethernet Pins906
-
MAC Interrupts930
-
MAC Filtering931
-
DMA Arbiter947
-
DMA Interrupts970
-
OTG_FS Introduction1021
-
OTG_FS Main Features1022
-
General Features1022
-
Host-Mode Features1023
-
OTG Full-Speed Core1024
-
Full-Speed OTG PHY1025
-
ID Line Detection1026
-
HNP Dual Role Device1026
-
SRP Dual Role Device1027
-
USB Peripheral1027
-
Peripheral States1028
-
Peripheral Endpoints1029
-
USB Host1031
-
SRP-Capable Host1032
-
USB Host States1032
-
Host Channels1034
-
Host Scheduler1035
-
SOF Trigger1036
-
Host Sofs1036
-
Peripheral Sofs1037
-
Power Options1037
-
USB Data Fifos1039
-
Peripheral Rx FIFO1039
-
Peripheral Tx Fifos1040
-
Host Rx FIFO1040
-
Host Tx Fifos1041
-
FIFO RAM Allocation1041
-
Device Mode1041
-
Host Mode1042
-
OTG_FS Interrupts1043
-
CSR Memory Map1045
-
Host-Mode Registers1072
-
(Otg_Fs_Pcgcctl)1105
-
OTG_FS Register Map1106
-
Core Initialization1113
-
Host Initialization1114
-
Operational Model1134
-
OTG_HS Introduction1159
-
OTG_HS Main Features1160
-
General Features1160
-
Host-Mode Features1161
-
High-Speed OTG PHY1162
-
OTG Dual-Role Device1163
-
ID Line Detection1163
-
HNP Dual Role Device1163
-
SRP Dual-Role Device1163
-
Peripheral States1164
-
Peripheral Endpoints1165
-
SRP-Capable Host1168
-
USB Host States1168
-
Host Channels1170
-
Host Scheduler1171
-
SOF Trigger1172
-
Host Sofs1172
-
Peripheral Sofs1173
-
USB_HS Power Modes1174
-
FIFO RAM Allocation1175
-
Peripheral Mode1175
-
Host Mode1175
-
OTG_HS Interrupts1176
-
CSR Memory Map1179
-
Host-Mode Registers1208
-
(Otg_Hs_Pcgcctl)1247
-
OTG_HS Register Map1248
-
Core Initialization1260
-
Host Initialization1261
-
DMA Mode1262
-
Mode1268
-
Operational Model1292
-
FSMC Main Features1317
-
Block Diagram1318
-
AHB Interface1319
-
General Timing Rules1326
-
FSMC Register Map1373
-
Debug Support (DBG)1375
-
Overview1375
-
SWJ Debug Port Pins1378
-
MCU Device ID Code1382
-
Boundary Scan TAP1382
-
Cortex™-M4F TAP1382
-
JTAG Debug Port1383
-
SW Debug Port1385
-
SW Protocol Sequence1385
-
SW-DP Registers1387
-
SW-AP Registers1388
-
Core Debug1390
-
General Description1392
-
General Description1394
-
Main ETM Registers1395
-
13961396
-
Introduction1400
-
TRACE Pin Assignment1401
-
TPUI Formatter1402
-
Synchronous Mode1403
-
Asynchronous Mode1404
-
TPIU Registers1405
-
DBG Register Map1406
-
Flash Size1408
-
Revision History1413
Advertisement
Advertisement