Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx (Rcc_Ahb1Lpenr) - ST STM32F40 Series Reference Manual

RM0090
6.3.19 RCC AHB1 peripheral clock enable in low power mode register
for STM32F405xx/07xx and STM32F415xx/17xx
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x7E67 91FF
Access: no wait state, word, half-word and byte access.
31 30 29
OTGHS OTGHS ETHPTP
Reser-
ULPILPEN LPEN LPEN
ved
rw rw
15 14 13
FLITF
LPEN LPEN
Reserved
rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode
Set and cleared by software.
0: USB OTG HS ULPI clock disabled during Sleep mode
1: USB OTG HS ULPI clock enabled during Sleep mode
Bit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode
Set and cleared by software.
0: USB OTG HS clock disabled during Sleep mode
1: USB OTG HS clock enabled during Sleep mode
Bit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode
Set and cleared by software.
0: Ethernet PTP clock disabled during Sleep mode
1: Ethernet PTP clock enabled during Sleep mode
Bit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode
Set and cleared by software.
0: Ethernet reception clock disabled during Sleep mode
1: Ethernet reception clock enabled during Sleep mode
Bit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode
Set and cleared by software.
0: Ethernet transmission clock disabled during sleep mode
1: Ethernet transmission clock enabled during sleep mode
Bit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode
Set and cleared by software.
0: Ethernet MAC clock disabled during Sleep mode
1: Ethernet MAC clock enabled during Sleep mode
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
28 27 26 25
ETHRX ETHTX ETHMAC
LPEN LPEN LPEN
rw rw rw rw
12 11 10 9
CRC
Reserved
rw
Doc ID 018909 Rev 4
Reset and clock control for (RCC)
24 23 22 21
DMA2 DMA1
LPEN LPEN
Reserved
rw rw
8 7 6 5
GPIOI GPIOH GPIOGG GPIOF
LPEN LPEN LPEN LPEN
rw rw rw rw
20 19 18
BKPSRA
SRAM2
M
LPEN
Reserved
LPEN
rw
4 3 2
GPIOE GPIOD GPIOC GPIOB
LPEN LPEN LPEN LPEN
rw rw rw
17 16
SRAM1
LPEN
rw rw
1 0
GPIOA
LPEN
rw rw
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