ST STM32F40 Series Reference Manual page 570

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Cryptographic processor (CRYP)

During the DES or TDES CBC encryption, the CRYP_IV0(L/R) bits are XORed with the 64-

bit data block popped off the IN FIFO after swapping (according to the DATATYPE value),

that is, with the M1...64 bits of the data block. When the output of the

available, it is copied back into the CRYP_IV0(L/R) vector, and this new content is XORed

with the next 64-bit data block popped off the IN FIFO, and so on.

During the DES or TDES CBC decryption, the CRYP_IV0(L/R) bits are XORed with the 64-

bit data block (that is, with the M1...64 bits) delivered by the

block before swapping

(according to the DATATYPE value), and pushed into the OUT FIFO. When the XORed

result is swapped and pushed into the OUT FIFO, the CRYP_IV0(L/R) value is replaced by

the output of the IN FIFO, then the IN FIFO is popped, and a new 64-bit data block can be

During the AES CBC encryption, the CRYP_IV0...1(L/R) bits are XORed with the 128-bit

data block popped off the IN FIFO after swapping (according to the DATATYPE value). When

the output of the AES core is available, it is copied back into the CRYP_IV0...1(L/R) vector,

and this new content is XORed with the next 128-bit data block popped off the IN FIFO, and

During the AES CBC decryption, the CRYP_IV0...1(L/R) bits are XORed with the 128-bit

data block delivered by the AES core before swapping (according to the DATATYPE value)

and pushed into the OUT FIFO. When the XORed result is swapped and pushed into the

OUT FIFO, the CRYP_IV0...1(L/R) value is replaced by the output of the IN FIFO, then the

IN FIFO is popped, and a new 128-bit data block can be processed.

During the AES CTR encryption or decryption, the CRYP_IV0...1(L/R) bits are encrypted by

the AES core. Then the result of the encryption is XORed with the 128-bit data block popped

off the IN FIFO after swapping (according to the DATATYPE value). When the XORed result

is swapped and pushed into the OUT FIFO, the counter part of the CRYP_IV0...1(L/R) value

(32 LSB) is incremented.

Any write operation to the CRYP_IV0...1(L/R) registers when bit BUSY = 1b in the

CRYP_SR register is disregarded (CRYP_IV0...1(L/R) register content not modified). Thus,

you must check that bit BUSY = 0b before modifying initialization vectors.

Doc ID 018909 Rev 4

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