Figure 137. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 138. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32F40 Series Reference Manual

General-purpose timers (TIM2 to TIM5)

Figure 137. Counter timing diagram, Update event with ARPE=1 (counter underflow)

Figure 138. Counter timing diagram, Update event with ARPE=1 (counter overflow)

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CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
Doc ID 018909 Rev 4
06 05 04 03 02 01 00 01 02 03 04 05 06 07
FD
FD
F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
FD
FD
RM0090
36
36
36
36