ST STM32F40 Series Reference Manual page 691

Controller area network (bxCAN)
CAN interrupt enable register (CAN_IER)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
15 14 13
ERRIE
Reserved
rw
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 SLKIE
Bit 16 WKUIE
Bit 15 ERRIE
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 LECIE
Bit 10 BOFIE
Bit 9 EPVIE
Bit 8 EWGIE
Bit 7 Reserved, must be kept at reset value.
Bit 6 FOVIE1
Bit 5 FFIE1
691/1422
28 27 26 25
Reserved
12 11 10 9
LEC BOF EPV
IE IE IE
rw rw rw
:
Sleep interrupt enable
0: No interrupt when SLAKI bit is set.
1: Interrupt generated when SLAKI bit is set.
:
Wakeup interrupt enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
:
Error interrupt enable
0: No interrupt will be generated when an error condition is pending in the CAN_ESR.
1: An interrupt will be generation when an error condition is pending in the CAN_ESR.
:
Last error code interrupt enable
0: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error
detection.
1: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection.
:
Bus-off interrupt enable
0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
:
Error passive interrupt enable
0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
:
Error warning interrupt enable
0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
:
FIFO overrun interrupt enable
0: No interrupt when FOVR is set.
1: Interrupt generation when FOVR is set.
:
FIFO full interrupt enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Doc ID 018909 Rev 4
24 23 22 21
8 7 6 5
EWG FOV FF
IE IE1 IE1
Res.
rw rw rw
20 19 18 17
SLKIE
rw
4 3 2 1
FMP FOV FF FMP
IE1 IE0 IE0 IE0
rw rw rw rw
RM0090
16
WKUIE
rw
0
TME
IE
rw