Cryp Status Register (Cryp_Sr) - ST STM32F40 Series Reference Manual

Cryptographic processor (CRYP)
Note: Writing to the KEYSIZE, DATATYPE, ALGOMODE and ALGODIR bits while BUSY=1 has no
effect. These bits can only be configured when BUSY=0.
The FFLUSH bit has to be set only when BUSY=0. If not, the FIFO is flushed, but the block
being processed may be pushed into the output FIFO just after the flush operation, resulting
in a nonempty FIFO condition.
20.6.3

CRYP status register (CRYP_SR)

Address offset: 0x04
Reset value: 0x0000 0003
31 30 29
15 14 13
581/1422
Bit 2 ALGODIR: Algorithm direction
0: Encrypt
1: Decrypt
Bit 1:0 Reserved, must be kept to 0.
28 27 26 25
12 11 10 9
Reserved
Bit 31:5 Reserved, must be kept at reset value
Bit 4 BUSY: Busy bit
0: The CRYP Core is not processing any data. The reason is either that:
– the CRYP core is disabled (CRYPEN=0 in the CRYP_CR register) and
the last processing has completed, or
– The CRYP core is waiting for enough data in the input FIFO or enough
free space in the output FIFO (that is in each case at least 2 words in
the DES, 4 words in the AES).
1: The CRYP core is currently processing a block of data or a key preparation
(for AES decryption).
Bit 3 OFFU: Output FIFO full
0: Output FIFO is not full
1: Output FIFO is full
Bits 2 OFNE: Output FIFO not empty
0: Output FIFO is empty
1: Output FIFO is not empty
Bit 1 IFNF: Input FIFO not full
0: Input FIFO is full
1: Input FIFO is not full
Bits 0 IFEM: Input FIFO empty
0: Input FIFO is not empty
1: Input FIFO is empty
Doc ID 018909 Rev 4
24 23 22 21
Reserved
8 7 6 5
20 19 18 17
4 3 2 1
BUSY OFFU OFNE IFNF
r r r
RM0090
16
0
IFEM
r r