Spi Status Register (Spi_Sr) - ST STM32F40 Series Reference Manual

RM0090
27.5.3

SPI status register (SPI_SR)

Address offset: 0x08
Reset value: 0x0002
15 14 13
Reserved
Bits 15:9 Reserved. Forced to 0 by hardware.
Bit 8 FRE: Frame format error
Note: This flag is used when the SPI operates in TI slave mode or I2S slave mode (refer to
Bit 7 BSY: Busy flag
Note: BSY flag must be used with caution: refer to
Bit 6 OVR: Overrun flag
Bit 5 MODF: Mode fault
Note: Not used in I
Bit 4 CRCERR: CRC error flag
Note: Not used in I
Bit 3 UDR: Underrun flag
Note: Not used in SPI mode
Bit 2 CHSIDE: Channel side
Note: Not used for SPI mode. No meaning in PCM mode
12 11 10 9
0: No frame format error
1: A frame format error occurred
This flag is set by hardware and cleared by software when the SPIx_SR register is read.
Section 27.3.10).
0: SPI (or I2S) not busy
1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Section 27.3.8: Disabling the
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
page 835 for the software sequence.
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
page 818 for the software sequence.
2
S mode
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
2
S mode
0: No underrun occurred
1: Underrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
page 835 for the software sequence.
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
Doc ID 018909 Rev 4
8 7 6 5
FRE BSY OVR MODF
r r r r
Section 27.3.7: Status flags
SPI.
Serial peripheral interface (SPI)
4 3 2
CRC CHSID
UDR
ERR E
rc_w0 r r
and
Section 27.4.8 on
Section 27.3.10 on
Section 27.4.8 on
1 0
TXE RXNE
r r
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